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MESC TOOL NEWS:
MESCT-MR30-000916D
Please take note of the following problem in using real-time OS:
- On setting the system timer in the M16C/6N MCU group
- Versions Concerned
All the versions of MR30
- Problem
The system clock timer may operate with the period twice longer than the system clock period set on the configuration file.
- Conditions
- This problem occurs if the following three conditions are satisfied:
- (1) The target MCU is of the M16C/6N group.
- (2) The divide-by-2 mode is selected by bit 0 of the peripheral function clock select register (address 25E). (The default is the divide-by-2 mode.)
- (3) The following relation holds.
- Period of timer clock (s) multiplied by Clock frequency (Hz) <= 65535
- Workaround
In the startup file, crt0mr.a30 or start.a30, add a program to the last of the instructions that specify MR30's system timer as shown below. This program divides the count source by 2 only when the divide-by-2 count source is selected by the count source select bits of the timer mode register; if the divide-by-8 or -32 count source is selected, nothing affected. Don't add the program if the divide-by-1 mode is selected by the peripheral function clock select register.
; +---------------------------------------------------------------------+
; | System timer interrupt setting |
; +---------------------------------------------------------------------+
mov.b #stmr_mod_val,stmr_mod_reg ;set timer mode
; mov.b #1H,0AH
; bset 6,07H
mov.b #stmr_int_IPL,stmr_int_reg ;set timer IPL
; bclr 6,07H
; mov.b #0,0AH
mov.w #stmr_cnt,stmr_ctr_reg ;set interval count
mov.b stmr_mod_reg,R0L ;Added
and.b #0C0H,R0L ;Added
jnz __MR_SYSTIME_END ;Added
mov.w #stmr_cnt/2,stmr_ctr_reg ;Added
__MR_SYSTIME_END: ;Added
or.b #stmr_bit+1,stmr_start ;system timer start
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