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MAEC TOOL NEWS:
MAECT-MR32R-010401D
Please take note of the following problems in using real-time OS for the M32R family of microcomputers:
- On using the vsnd_mbx and visnd_mbx system calls
- On using linker command file m32r.cmd of the D-CC/M32R compiler manufactured by Wind River Systems, Inc.
- The Problems on Using the vsnd_mbx and visnd_mbx System Calls
- 1.1 The Versions Concerned
- MR32R V.3.20 Release 1 -- MR32R V.3.30 Release 1
- 1.2 Descriptions
- Problem 1
The task whose priority has been altered would receive no messages the task is waiting for, so the waiting state of the task is not removed.
[Conditions]
This problem occurs if the following five conditions are satisfied:
- (a) The attribute of the mailbox from which the task receives messages is set to TA_TPRI.
- (b) An interrupt was requested during processing the vsnd_mbx or visnd_mbx system call.
- (c) The handler invoked by the interrupt in (b) has issued the ichg_pri system call.
- (d) The ichg_pri system call has altered the task's priority from low to high.
- (e) The mailbox ID of the mailbox that the task whose priority was changed in (d) is waiting for and the one that system call vsnd_mbx or visnd_mbx in (b) takes as an argument are the same.
- Problem 2
No messages can properly be transmitted when the visnd_mbx system call is issued.
[Conditions]
This problem occurs if the following five conditions are satisfied:
- (a) The attribute of the mailbox is set to TA_MPRI.
- (b) More than 14 messages are stored in the mailbox.
- (c) An interrupt was requested during processing the vsnd_mbx or visnd_mbx system call.
- (d) The handler invoked by the interrupt in (c) has issued the visnd_mbx system call.
- (e) The mailbox ID that system call vsnd_mbx or visnd_mbx in (c) takes as an argument and the one that system call visnd_mbx in (d) does are the same.
- 1.3 Workaround
- Disable interrupts before processing the vsnd_mbx or visnd_mbx system call, and enable them after processing it.
Example 1: Disabling and enabling interrupts
by using loc_cpu() and unl_cpu() respectively
---------------------------------------------------------------------
void task(stacd)
{
:
loc_cpu(); /* Disables interrupts */
ercd = vsnd_mbx(ID_mbx,(T_MSG )&pmsg);
unl_cpu(); /* Enables interrupts */
:
}
---------------------------------------------------------------------
Example 2: Disabling and enabling interrupts by using the asm function
---------------------------------------------------------------------
void int_handler(void)
{
:
/* Disables interrupts */
asm(" mvfc R0,PSW\n"
" and3 R0,R0,#0xFFBF\n"
" mvtc R0,PSW\n");
ercd = visnd_mbx(ID_mbx,(T_MSG )&pmsg);
/* Enables interrupts */
asm(" mvfc R0,PSW\n"
" or3 R0,R0,#0x0040\n"
" mvtc R0,PSW\n");
:
}
---------------------------------------------------------------------
- 1.4 The Schedule of Fixing the Problems
- We plan to fix these problems in our next release.
- The Problem on Using Linker Command File m32r.cmd of the D-CC/M32R Compiler Manufactured by Wind River Systems, Inc.
- 2.1 The Versions Concerned
- MR32R V.3.20 Release 1 -- MR32R V.3.30 Release 1
- 2.2 Descriptions
- When COMMON variables * are used within the program, __END_bss labels do not indicate the end address of .bss sections.
So, when .bss section is initialized by zero using the RAM_CLEAR macro in the startup routine, the area assigned to COMMON variables is not initialized.
- [Note:]
* For information on the COMMON variable, see D-CC/M32R's document.
- 2.3 Workaround
- Modify linker command file m32r.cmd as shown below.
Modified:
---------------------------
.bss : {
__START_bss = .;
*(.sbss)
*(.bss)
*[COMMON] /* Added */
__END_bss = .;
}
---------------------------
Original:
---------------------------
.bss : {
__START_bss = .;
*(.sbss)
*(.bss)
__END_bss = .;
}
---------------------------
- 2.4 The Schedule of Fixing the Problem
- We plan to fix this problem in our next release.
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