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MAEC TOOL NEWS:
MAECT-M30620T2-RPD-E-011001D
Revised Precaution
Settings of the Multiplexed Bus Space Select Bits
in Emulation Pods for the M16C/62, M16C/6N,
M16C/6V, and M16C/6H Group MCUs
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This is a revision of MAEC TOOL NEWS "Precaution Settings of the Multiplexed Bus Space Select Bits in Emulation Pods for the M16C/62, M16C/6N, M16C/6V, and M16C/6H Group MCUs".
- Products Concerned
For the M16C/62 group MCUs
(See Note) |
M30620T-RPD-E, M30620T-RPD
M30620TB-RPD-E, M30620TB-RPD
M30620T2-RPD-E
M30620TL-RPD-E |
| For the M16C/6N group MCUs |
M306N0TB-RPD-E
M306N0T2-RPD-E |
| For the M16C/6V group MCUs |
M306V0T-RPD-E, M306V0T-RPD
M306V2T-RPD-E, M306V2T-RPD |
| For the M16C/6H group MCUs |
M306H0T-RPD-E, M306H0T-RPD
M306H1T-RPD-E, M306H1T-RPD |
(Note) The pods for the M16C/62 group MCUs remodeled from those for the M16C/60 and M16C/61 group are excluded.
- Problem
- When the processor mode "0" register (PM0) is set to use the multiplexed bus according to the steps shown in the MAEC TOOL NEWS "Precaution Settings of the Multiplexed Bus Space Select Bits in Emulation Pods for the M16C/62, M16C/6N, M16C/6V, and M16C/6H Group MCUs", emulator debugger M3T-PD30 will not properly perform the displays and functions described below.
- (1) The following debug functions at accessing the multiplexed bus space:
- Display in the Trace window
- Display in the RAM Monitor window
- Hardware break function
- (2) Microcomputer's memory space expansion function
- Workaround
- Run your emulation pod in single chip mode (the CNVss pin pulled to Vss); then, if you use the multiplexed bus, set the processor mode "0" register (PM0) in the following steps, using emulator debugger M3T-PD30:
- Step 1. Download the program
- Step 2. In the line where the settings of the multiplexed bus space select bits are made for the first time using the Program or Dump window, establish the settings of the processor mode bits simultaneously.
[Example of Step 2]
Modified:
-----------------------------------------------
START: LDC #2C00H,ISP
BSET 1,000AH
MOV.B #031H,0004H <- Here are made the settings of the
BSET 0,0004H processor mode bits simultaneously.
MOV.B #0,0005H
-----------------------------------------------
Original:
-----------------------------------------------
START: LDC #2C00H,ISP
BSET 1,000AH
MOV.B #030H,0004H <- Here are made the settings of the
BSET 0,0004H multiplexed bus space select bits.
MOV.B #0,0005H
-----------------------------------------------
- Caution
The above method of setting the processor mode register can be applied only when you use the emulation pod. When running actual MCUs, do not establish the settings of both the multiplexed bus space select bits and the processor mode bits at a time.
Also check to make sure that the multiplexed bus operates properly on the actual MCU with on-chip flash memory.
For further information refer to MAEC TECHNICAL NEWS No.M16C-71-0105 (32KB in PDF).
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