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MESC TOOL NEWS:
MESCT-M30800T-RPD-E-991001D
Precaution
in
Using INT Instruction in M30800T-RPD-E
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Please take note of the following problem in using the INT instruction in the MCU mounted on emulation pod M30800T-RPD-E for the M16C/80 group of microcomputers.
- Products Concerned
| Product Name | Lot No. |
| M30800T-RPD-E | 9BR001 -- 9BR030/A
9CR031 -- 9CR080/A
9FR081 -- 9FR140A
9GR141 -- 9GR170A
9IR171 -- 9IR190A
9JR191 -- 9JR210A |
- Problem
When a software interrupt is generated by an INT instruction, the processor interrupt priority level (IPL) in the flag register (FLG) becomes indeterminate in the interrupt routine. However, the IPL restores its correct value after the interrupt by the INT instruction is complete. Only the interrupt generated by an INT instruction places the IPL in an indeterminate state.
Note : This problem is described in MESC Technical News No. M16C-37-9910 "Note on Using INT Instruction in M16C/80 Group MCUs" issued on October 1, 1999, and this item of MESC TOOL NEWS provides additional information necessary to
use M30800T-RPD-E.
- Workaround
This problem does not occur when the interrupt generated by an INT instruction is not enabled (the I flag set to 1) in its routine because IPL restores the normal level after the interrupt is complete. To enable other interrupts in an INT instruction interrupt routine, the following measures are necessary;
- 2.1 When the IPL value at the execution of an INT instruction is known, set IPL to that value by a LDIPL instruction.
- 2.2 Otherwise, read out the IPL value saved on the stack and set IPL to that value.
- To enable other interrupts within a non-maskable interrupt that has been generated in an INT instruction interrupt routine, re-set IPL in this routine.
- Non-maskable interrupts necessitating re-setting of IPL are as follows:
- Address match, BRK instruction, overflow, and undefined instruction interrupts (NMI and watchdog timer interrupts are excluded since IPL is set to 7 in these interrupts).
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