Immediate

#IMM:1

#IMM:3

#IMM:4

#UIMM:4

#IMM:5

#IMM:1

The operand is the 1-bit immediate value indicated by #IMM. This addressing mode is used to specify the source for the RACW instruction.

#IMM:3

The operand is the 3-bit immediate value indicated by #IMM. This addressing mode is used to specify the bit number for the bit manipulation instructions: BCLR, BMCnd, BNOT, BSET, and BTST.

#IMM:4

The operand is the 4-bit immediate value indicated by #IMM. This addressing mode is used to specify the interrupt priority level for the MVTIPL instruction.

#UIMM:4

The operand is the 4-bit immediate value indicated by #UIMM after zero extension to 32 bits. This addressing mode is used to specify sources for ADD, AND, CMP, MOV, MUL, OR, and SUB instructions.

#IMM:5

The operand is the 5-bit immediate value indicated by #IMM. This addressing mode is used in the following ways:

- to specify the bit number for the bit-manipulation instructions: BCLR, BMCnd, BNOT, BSET, and BTST;

- to specify the number of bit places of shifting in certain arithmetic/logic instructions: SHAR, SHLL, and SHLR; and

- to specify the number of bit places of rotation in certain arithmetic/logic instructions: ROTL and ROTR.

Immediate

#IMM:8

#SIMM:8

#UIMM:8

#IMM:16

#SIMM:16

#SIMM:24

#IMM:32

The specified register is the object of the operation.

Register Direct

Rn

(Rn = R0 to R15)

The operand is the specified register. In addition, the Rn value is transferred to the program counter (PC) when this addressing mode is used with JMP and JSR instructions. The range of valid addresses is from 00000000h to FFFFFFFFh. Rn (Rn = R0 to R15) can be specified.

Register Indirect

[Rn]

(Rn = R0 to R15)

The value in the specified register is the effective address of the operand. The range of valid addresses is from 00000000h to FFFFFFFFh. [Rn] (Rn = R0 to R15) can be specified.

Register Relative

dsp:5[Rn]

(Rn = R0 to R7)

dsp:8[Rn]

(Rn = R0 to R15)

dsp:16[Rn]

(Rn = R0 to R15)

The effective address of the operand is the least significant 32 bits of the sum of the displacement (dsp) value, after zero-extension to 32 bits and multiplication by 1, 2, or 4 according to the specification (see the diagram at right), and the value in the specified register. The range of valid addresses is from 00000000h to FFFFFFFFh. dsp:n represents an n-bit long displacement value. The following mode can be specified:

dsp:5[Rn] (Rn = R0 to R7),

dsp:8[Rn] (Rn = R0 to R15), and

dsp:16[Rn] (Rn = R0 to R15).

dsp:5[Rn] (Rn = R0 to R7) is used only with MOV and MOVE instructions.

Post-increment Register Indirect

[Rn+]

(Rn = R0 to R15)

The value in the specified register is the effective address of the operand. The range of valid addresses is from 00000000h to FFFFFFFFh. After the operation, 1, 2, or 4 is added to the value in the specified register according to the size specifier: .B, .W, or .L. This addressing mode is used with MOV and MOVU instructions.

Pre-decrement Register Indirect

[-Rn]

(Rn = R0 to R15)

According to the size specifier: .B, .W, or .L, 1, 2, or 4 is subtracted from the value in the specified register. The value after the operation is the effective address of the operand. The range of valid addresses is from 00000000h to FFFFFFFFh. This addressing mode is used with MOV and MOVU instructions.

Indexed Register Indirect

[Ri,Rb]

(Ri = R0 to R15, Rb = R0 to R15)

The effective address of the operand is the least significant 32 bits of the sum of the value in the index register (Ri), multiplied by 1, 2, or 4 according to the size specifier: .B, .W, or .L, and the value in the base register (Rb). The range of valid addresses is from 00000000h to FFFFFFFFh. This addressing mode is used with MOV and MOVU instructions.

Control Register Direct

PC

ISP

USP

INTB

PSW

BPC

BPSW

FINTV

FPSW

The operand is the specified control register. This addressing mode is used with MVFC, MVTC, POPC, and PUSHC instructions.

The PC is only selectable as the src operand of MVFC and PUSHC instructions.

PSW Direct

C

Z

S

O

I

U

The operand is the specified flag or bit. This addressing mode is used with CLRPSW and SETPSW instructions.

Program Counter Relative

pcdsp:3

When the branch distance specifier is .S, the effective address is the least significant 32 bits of the unsigned sum of the value in the program counter (PC) and the displacement (pcdsp) value. The range of the branch is from 3 to 10. The range of valid addresses is from 00000000h to FFFFFFFFh. This addressing mode is used with BCnd (where Cnd==EQ/Z or NE/NZ) and BRA instructions.

Program Counter Relative

pcdsp:8

pcdsp:16

pcdsp:24

When the branch distance specifier is .B, .W, or .A, the effective address is the signed sum of the value in the program counter (PC) and the displacement (pcdsp) value. The range of pcdsp depends on the branch distance specifier.

For .B: -128 ? pcdsp:8 ? 127

For .W: -32768 ? pcdsp:16 ? 32767

For .A: -8388608 ? pcdsp:24 ? 8388607

The range of valid addresses is from 00000000h to FFFFFFFFh. When the branch distance specifier is .B, this addressing mode is used with BCnd and BRA instructions. When the branch distance specifier is .W, this addressing mode is used with BCnd (where Cnd==EQ/Z or NE/NZ), BRA, and BSR instructions. When the branch distance specifier is .A, this addressing mode is used with BRA and BSR instructions.

Program Counter Relative

Rn

(Rn = R0 to R15)

The effective address is the signed sum of the value in the program counter (PC) and the Rn value. The range of the Rn value is from -2147483648 to 2147483647. The range of valid addresses is from 00000000h to FFFFFFFFh. This addressing mode is used with BRA(.L) and BSR(.L) instructions.