19.19 Fixed Vector/Exception Vector Information (interrupt_fvector[])

Here, fixed vector table of the RXv1 architecture (address from 0xFFFFFF80 to 0xFFFFFFFF) / exception vector table of RXv2 architecture is defined.

Not only interrupt handler address but also the endian select register, etc., are included in fixed vector table/exception vector table.

All interrupt in fixed vector/exception vector is non-kernel interrupt.

In the RI600V4, the vector number is allocated according to the vector address as shown in Table 19-10. Table 19-10 also shows the setting of the vector to which the definition is omitted.

Note, the content of fixed vector table/exception vector table is different in each MCU. For details, refer to the hardware manual of the MCU used.

Note, the cfg600 does not generate code to initialize the interrupt control registers, the causes of interrupts, etc. for the interrupts defined here. These initialization need to be implemented in the application.

Table 19-10 Fixed Vector Table/Exception Vector table

Vector address 1	Vector number	Example of factor (different in each MCU)	When omitting
0xFFFFFF80	0	Endian select register	The following are set according to "-endian" compiler option. - "-endian=little" 0xFFFFFFFF - "-endian=big" 0xFFFFFFF8
0xFFFFFF84	1	(Reserved area)	0xFFFFFFFF
0xFFFFFF88	2	Option function select register 1
0xFFFFFF8C	3	Option function select register 0
0xFFFFFF90	4	(Reserved area)
0xFFFFFF94	5	(Reserved area)
0xFFFFFF98	6	(Reserved area)
0xFFFFFF9C	7	ROM code protection (flash memory)
0xFFFFFFA0	8	ID code protection on connection of the on-chip debugger (flash memory)
0xFFFFFFA4	9
0xFFFFFFA8	10
0xFFFFFFAC	11
0xFFFFFFB0	12	(Reserved area)
0xFFFFFFB4	13	(Reserved area)
0xFFFFFFB8	14	(Reserved area)
0xFFFFFFBC	15	(Reserved area)
0xFFFFFFC0	16	(Reserved area)	System down
0xFFFFFFC4	17	(Reserved area)
0xFFFFFFC8	18	(Reserved area)
0xFFFFFFCC	19	(Reserved area)
0xFFFFFFD0	20	Privileged instruction exception
0xFFFFFFD4	21	Access exception
0xFFFFFFD8	22	(Reserved area)
0xFFFFFFDC	23	Undefined instruction exception
0xFFFFFFE0	24	(Reserved area)
0xFFFFFFE4	25	Floating-point exception
0xFFFFFFE8	26	(Reserved area)
0xFFFFFFEC	27	(Reserved area)
0xFFFFFFF0	28	(Reserved area)
0xFFFFFFF4	29	(Reserved area)
0xFFFFFFF8	30	Non-maskable interrupt
0xFFFFFFFC	31	Reset	PowerON_Reset_PC()

1 The vector address in Table 19-10 is the address of fixed vector table in RXv1 architecture. The address of exception vector table in RXv2 architecture is decided by EXTB register. The initial value of EXTB register at the time of reset is same as fixed vector table in RXv1 architecture. Refer to "FIX_INTERRUPT_VECTOR section" in section 2.6.4.

Format

Parentheses < >show the user input part.

interrupt_fvector[ <1. Vector number> ] { entry_address = <2. Interrupt handler entry address (entry_addreess)>; pragma_switch = <3. Switch passed to pragma directive (pragma_switch)>; };

1 ) Vector number

- Description
Define the vector number.

- Definition format
Numeric value

- Definition range
From 0 to 31

- When omitting
Cannot be omitted.

2 ) Interrupt handler entry address (entry_addreess)

- Description
Define the starting function of the interrupt handler or the set value to fixed vector/exception vector.

- Definition format
Symbol or numeric value

- Definition range
From 0 to 0xFFFFFFFF when a numeric value is specified.

- When omitting
Cannot be omitted.

3 ) Switch passed to pragma directive (pragma_switch)

- Description
The cfg600 outputs "#pragma interrupt" directive to handle the function specified by entry_address as a interrupt function to the system information header file kernel_id.h.
The switches passed to this pragma directive should be specified for pragma_switch.

- Definition format
Symbol

- Definition range
The following can be specified. To specify multiple choices, separate each with a comma. However, "ACC" and "NOACC" cannot be specified at the same time.

S: The "save" switch that limits the number of registers used in the interrupt handler is passed.

ACC: The "acc" switch that guarantees the ACC register in the interrupt handler is passed.

NOACC: The "no_acc" switch that does not guarantee the ACC register in the interrupt handler is passed

- When omitting
No switches are passed.

- Note
Refer to Table 19-9 for the guarantee of the ACC register.