Five types of numeric values described below can be written in programs.

The written values are handled as 32-bit signed values (except floating-point values).

Use digits 0 and 1, and append B or b as a suffix.

1011000B

1011000b

Use digits 0 to 7, and append O or o as a suffix.

60702O

60702o

Use digits 0 to 9.

9243

Use digits 0 to 9 and letters A to F and a to f, and append H or h as a suffix.

When starting with a letter, append 0 as a prefix.

0A5FH

5FH

0a5fh

5fh

A floating-point number can be written only as the operand of the .FLOAT or .DOUBLE directive.

No floating-point number can be used in expressions.

The following range of values can be written as floating-point numbers.

FLOAT (32 bits): 1.17549435 * 10-38 to 3.40282347 * 1038
DOUBLE (64 bits): 2.2250738585072014 * 10-308 to 1.7976931348623157 * 10308

(mantissa)E(exponent)

(mantissa)e(exponent)

3.4E35	        ;3.4*10**35

3.4e-35	       ;3.4*10**-35

-.5E20        	;-0.5*10**20

5e-20	         ;5.0*10**-20

The following three types of addressing mode can be specified in operands.

The specified register is the object of operation. R0 to R15 and SP can be specified. SP is assumed as R0 (R0 = SP).

Rn (Rn=R0 to R15, SP)

ADD  R1, R2

#imm indicates an immediate integer.

#uimm indicates an immediate unsigned integer.

#simm indicates an immediate signed integer.

#imm:n, #uimm:n, and #simm:n indicate an n-bit immediate value.

#imm:8, #uimm:8, #simm:8, #imm:16, #simm:16, #simm:24, #imm:32

MOV.L  #-100, R2	; #simm:8

The value in the register indicates the effective address of the object of operation. The effective address range is 00000000h to FFFFFFFFh.

[Rn] (Rn=R0 to R15, SP)

ADD  [R1], R2

The effective address of the object of operation is the sum of the displacement (dsp) after zero-extension to 32 bits and the register value. The effective address range is 00000000h to FFFFFFFFh. dsp:n represents an n-bit displacement.

Specify a dsp value scaled with the following rules. The assembler restores it to the value before scaling and embeds it into the instruction bit pattern.

dsp:8[Rn], dsp:16[Rn] (Rn=R0 to R15, SP)

ADD  400[R1], R2	; dsp:8[Rn] (400/4 = 100)

When the size specifier is W or L but the address is not a multiple of 2 or 4:

if the value is determined at assembly: Error at assembly

if the value is not determined at assembly: Error at linkage

The immediate value specified by #imm is the object of operation. When the immediate value is not determined at assembly, an error will be output.

#imm:1

This addressing mode is used only for src in the DSP function instruction (RACW). 1 or 2 can be specified as an immediate value.

Example:

RACW  #1		; RACW  #imm:1

#imm:2

The 2-bit immediate value specified by #imm is the object of operation. This addressing mode is only used to specify the coprocessor number in coprocessor instructions (MVFCP, MVTCP, and OPECP).

Example:

MVTCP  #3, R1, #4:16	; MVTCP  #imm:2, Rn, #imm:16

#imm:3

The 3-bit immediate value specified by #imm is the object of operation. This addressing mode is used to specify the bit number in bit manipulation instructions (BCLR, BMCnd, BNOT, BSET, and BTST).

Example:

BSET   #7, R10	; BSET   #imm:3, Rn

#imm:4

When using this addressing mode in the source statements of the ADD, AND, CMP, MOV, MUL, OR, and SUB instructions, the object of operation is obtained by zero-extension of the 4-bit immediate value specified by #imm to 32 bits.

When using this addressing mode to specify the interrupt priority level in the MVTIPL instruction, the object of operation is the 4-bit immediate value specified by #imm.

Example:

ADD   #15, R8	; ADD   #imm:4, Rn

#imm:5

The 5-bit immediate value specified by #imm is the object of operation. This addressing mode is used to specify the bit number in bit manipulation instructions (BCLR, BMCnd, BNOT, BSET, and BTST), the number of bits shifted in shift instructions (SHAR, SHLL, and SHLR), and the number of bits rotated in rotate instructions (ROTL and ROTR).

Example:

BSET  #31, R10	; BSET   #imm:5, Rn

The effective address of the object of operation is the sum of the 5-bit displacement (dsp) after zero-extension to 32 bits and the register value. The effective address range is 00000000h to FFFFFFFFh.

Specify a dsp value respectively multiplied by 1, 2, or 4 according to the size specifier (.B, .W, or .L). The assembler restores it to the value before scaling and embeds it into the instruction bit pattern. When the dsp value is not determined at assembly, an error will be output. This addressing mode is used only in the MOV and MOVU instructions.

dsp:5[Rn] (Rn=R0 to R7, SP)

Example:

MOV.L  R3,124[R1]	; dsp:5[Rn] (124/4 = 31)

1, 2, or 4 is respectively added to the register value according to the size specifier (.B, .W, or .L). The register value before increment is the effective address of the object of operation. The effective address range is 00000000h to FFFFFFFFh. This addressing mode is used only in the MOV and MOVU instructions.

[Rn+] (Rn=R0 to R15, SP)

Example:

MOV.L [R3+],R1

1, 2, or 4 is respectively subtracted from the register value according to the size specifier (.B, .W, or .L). The register value after decrement is the effective address of the object of operation. The effective address range is 00000000h to FFFFFFFFh. This addressing mode is used only in the MOV and MOVU instructions.

[-Rn] (Rn=R0 to R15, SP)

Example:

MOV.L [-R3],R1

The effective address of the object of operation is the least significant 32 bits of the sum of the value in the index register (Ri) after multiplication by 1, 2, or 4 according to the size specifier (.B, .W, or .L) and the value in the base register (Rb). The effective address range is 00000000h to FFFFFFFFh. This addressing mode is used only in the MOV and MOVU instructions.

[Ri,Rb] (Ri=R0 to R15, SP)  (Rb=R0 to R15, SP)

Examples:

MOV.L [R3,R1],R2

MOV.L R3, [R1,R2]

The specified control register is the object of operation.

This addressing mode is used only in the MVTC, POPC, PUSHC, and MVFC instructions.

PSW, FPSW, USP, ISP, INTB, BPSW, BPC, FINTV, PC, CPEN

Example:

STC  PSW,R2

The specified flag or bit is the object of operation. This addressing mode is used only in the CLRPSW and SETPSW instructions.

U, I, O, S, Z, C

Example:

CLRPSW  U

This addressing mode is used to specify the branch destination in the branch instruction.

Rn (Rn=R0 to R15, SP)

The effective address is the signed sum of the program counter value and the Rn value. The range of the Rn value is –2147483648 to 2147483647. The effective address range is 00000000h to FFFFFFFFh. This addressing mode is used in the BRA(.L) and BSR(.L) instructions.

label(PC + pcdsp:3)

This specifies the destination address of a branch instruction. The specified symbol or value indicates the effective address.

The assembler subtracts the program counter value from the specified branch destination address and embeds it into the instruction bit pattern as a displacement (pcdsp).

When the branch distance specifier is .S, the effective address is the least significant 32 bits of the unsigned sum of the program counter value and the displacement value.

The range of pcdsp is 3 ≤ pcdsp:3 ≤ 10.

The effective address range is 00000000h to FFFFFFFFh. This addressing mode is used only in the BRA and BCnd (only for Cnd == EQ, NE, Z, or NZ) instructions.

label(PC + pcdsp:8/pcdsp:16/pcdsp:24)

This specifies the destination address of a branch instruction. The specified symbol or value indicates the effective address.

The assembler subtracts the program counter value from the specified branch destination address and embeds it into the instruction bit pattern as a displacement (pcdsp).

When the branch distance specifier is .B, .W, or .A, the effective address is the least significant 32 bits of the signed sum of the program counter value and the displacement value. The range of pcdsp is as follows.

For .B: –128 ≤ pcdsp:8 ≤ +127

For .W: –32768 ≤ pcdsp:16 ≤ +32767

For .A: –8388608 ≤ pcdsp:24 ≤ +8388607

The effective address range is 00000000h to FFFFFFFFh.

A bit length specifier specifies the size of the immediate value or displacement in the operand.

:width

This specifier should be appended immediately after the immediate value or displacement specified in the operand.

The assembler selects an addressing mode according to the specified size.

When this specifier is omitted, the assembler selects the optimum bit length for code efficiency.

When specified, the assembler does not select the optimum size but uses the specified size.

This specifier must not be used for operands of assembler directives.

One or more space characters can be inserted between an immediate value or a displacement and this specifier.

When a size specified for an instruction is not allowed for that instruction, an error will be output.

The following can be specified as width.

2: Indicates an effective length of one bit.

#imm:2

3: Indicates an effective length of three bits.

#imm:3

4: Indicates an effective length of four bits.

#imm:4

5: Indicates an effective length of five bits.

#imm:5, dsp:5

8: Indicates an effective length of eight bits.

#uimm:8, #simm:8, dsp:8

16: Indicates an effective length of 16 bits.

#uimm:16, #simm:16, dsp:16

24: Indicates an effective length of 24 bits.

#simm:24

32: Indicates an effective length of 32 bits.

#imm:32

A size extension specifier specifies the size of a memory operand and the type of extension when memory is specified as the source operand of an arithmetic/logic instruction.

.memex

This specifier should be appended immediately after a memory operand and no space character should be inserted between them.

Size extension specifiers are valid only for combinations of specific instructions and memory operands; if a size extension specifier is used for an invalid combination of instruction and operand, an error will be output.

Valid combinations are indicated by ".memex" appended after the source operands in the Instruction Format description of the RX Family Software Manual.

When this specifier is omitted, the assembler assumes B for bit manipulation instructions or assumes L for other instructions.

The following shows available size extension specifiers and their function.

Examples:

ADD  [R1].B, R2

AND  125[R1].UB, R2