This function displays a break condition.
[Specification format]
debugger.GetBreakStatus()
|
[Argument(s)]
None
[Return value]
Break-trigger string (See [Detailed description])
Remark 1. | Returns the string portion of the "BreakStatus" enum. |
Remark 2. | Determine conditions by writing in the format "BreakStatus.string". |
[Detailed description]
- | This function displays break-trigger.
During execution, this will be "None". |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
None
|
No break
|
|
|
|
|
|
|
|
|
|
|
Manual
|
Forced break
|
|
|
|
|
|
|
|
|
|
|
Event
|
Break due to event
|
|
|
|
|
|
|
|
|
|
|
Software
|
Software break
|
|
|
|
|
|
|
|
|
|
|
TraceFull
|
Break due to trace full
|
|
|
|
|
|
|
|
|
|
|
TraceDelay
|
Break due to trace delay
|
|
|
|
|
|
|
|
|
|
|
NonMap
|
Access to non-mapped area
|
|
|
|
|
|
|
|
|
|
|
WriteProtect
|
Write to write-protected area
|
|
|
|
|
|
|
|
|
|
|
ReadProtect
|
Read from read-protected area
|
|
|
|
|
|
|
|
|
|
|
SfrIllegal
|
Illegal SFR access
|
|
|
|
|
|
|
|
|
|
|
SfrReadProtect
|
Read from non-readable SFR
|
|
|
|
|
|
|
|
|
|
|
SfrWriteProtect
|
Write to non-writable SFR
|
|
|
|
|
|
|
|
|
|
|
IorIllegal
|
Illegal access to peripheral I/O register (with address)
|
|
|
|
|
|
|
|
|
|
|
StackOverflow
|
Break due to stack overflow
|
|
|
|
|
|
|
|
|
|
|
StackUnderflow
|
Break due to stack underflow
|
|
|
|
|
|
|
|
|
|
|
UninitializeStackPointer
|
Break due to uninitialized stack pointer
|
|
|
|
|
|
|
|
|
|
|
UninitializeMemoryRead
|
Read uninitialized memory
|
|
|
|
|
|
|
|
|
|
|
TimerOver
|
Execution timeout detected
|
|
|
|
|
|
|
|
|
|
|
UnspecifiedIllegal
|
Illegal operation in user program relating to peripheral chip features
|
|
|
|
|
|
|
|
|
|
|
ImsIxsIllegal
|
Break due to illegal write to IMS/IXS register
|
|
|
|
|
|
|
|
|
|
|
BeforeExecution
|
Pre-execution break
|
|
|
|
|
|
|
|
|
|
|
SecurityProtect
|
Accessed security-protected region
|
|
|
|
|
|
|
|
|
|
|
FlashMacroService
|
Flash macro service active
|
|
|
|
|
|
|
|
|
|
|
RetryOver
|
Number of retries exceeded limit
|
|
|
|
|
|
|
|
|
|
|
FlashIllegal
|
Illegal Flash break
|
|
|
|
|
|
|
|
|
|
|
Peripheral
|
Break from peripheral
|
|
|
|
|
|
|
|
|
|
|
WordMissAlignAccess
|
Word access to odd address
|
|
|
|
|
|
|
|
|
|
|
Temporary
|
Temporary break
|
|
|
|
|
|
|
|
|
|
|
Escape
|
Escape break
|
|
|
|
|
|
|
|
|
|
|
Fetch
|
Fetched from guard area or area where fetches are prohibited
|
|
|
|
|
|
|
|
|
|
|
IRamWriteProtect
|
Wrote to IRAM guard area (with address)Note 3
|
|
|
|
|
|
|
|
|
|
|
IllegalOpcodeTrap
|
Break due to illegal instruction exception
|
|
|
|
|
|
|
|
|
|
|
Step
|
Step execution breakNote 4
|
|
|
|
|
|
|
|
|
|
|
FetchGuard
|
Fetch guard breakNote 4
|
|
|
|
|
|
|
|
|
|
|
TraceStop
|
Trace stopNote 4
|
|
|
|
|
|
|
|
|
|
|
ExecutionFails
|
Execution failedNote 5
|
|
|
|
|
|
|
|
|
|
|
Note 1. | Applies to all of the following: MINICUBE2, E1Serial, and E20Serial. |
Note 2. | Applies to all of the following: MINICUBE, E1Jtag, E20Jtag, and MINICUBE2Jtag. |
Note 3. | Performed a verification check on the IRAM guard area during break, and the value was overwritten (if this affects multiple addresses, only the first address is shown). |
Note 4. | This is only a break cause during trace. |
Note 5. | This is only a break cause during a break. |
Note 6. | Not displayed with V850-MINICUBE on V850E/ME2, etc. (same core) when a post-execution event is used. |
|
|
|
|
|
|
|
|
|
|
|
|
|
None
|
No break
|
|
|
|
|
|
|
|
|
Manual
|
Forced break
|
|
|
|
|
|
|
|
|
Event
|
Break due to event
|
|
|
|
|
|
|
|
|
Software
|
Software break
|
|
|
|
|
|
|
|
|
TraceFull
|
Break due to trace full
|
|
|
|
|
|
|
|
|
NonMap
|
Access to non-mapped area
|
|
|
|
|
|
|
|
|
WriteProtect
|
Write to write-protected area
|
|
|
|
|
|
|
|
|
TimerOver
|
Execution timeout detected
|
|
|
|
|
|
|
|
|
FlashMacroService
|
Flash macro service active
|
|
|
|
|
|
|
|
|
Temporary
|
Temporary break
|
|
|
|
|
|
|
|
|
IllegalOpcodeTrap
|
Break due to illegal instruction exception
|
|
|
|
|
|
|
|
|
Step
|
Step execution breakNote 3
|
|
|
|
|
|
|
|
|
ExecutionFails
|
Execution failedNote 4
|
|
|
|
|
|
|
|
|
WaitInstruction
|
Break caused by executing WAIT instruction
|
|
|
|
|
|
|
|
|
UndefinedInstructionException
|
Break caused by undefined instruction exception
|
|
|
|
|
|
|
|
|
PrivilegeInstructionException
|
Break caused by privileged instruction exception
|
|
|
|
|
|
|
|
|
AccessException
|
Break caused by access exception
|
|
|
|
|
|
|
|
|
FloatingPointException
|
Break caused by floating point exception
|
|
|
|
|
|
|
|
|
InterruptException
|
Break caused by interrupt
|
|
|
|
|
|
|
|
|
IntInstructionException
|
Break caused by INT instruction exception
|
|
|
|
|
|
|
|
|
BrkInstructionException
|
Break caused by BRK instruction exception
|
|
|
|
|
|
|
|
|
IOFunctionSimulationBreak
|
Break caused by peripheral function simulation
|
|
|
|
|
|
|
|
|
IllegalMemoryAccessBreak
|
Break caused by illegal memory access
|
|
|
|
|
|
|
|
|
StreamIoError
|
Break caused by stream I/O error
|
|
|
|
|
|
|
|
|
CoverageMemoryAllocationFailure
|
Failed to allocate coverage memory
|
|
|
|
|
|
|
|
|
TraceMemoryAllocationFailure
|
Failed to allocate trace memory
|
|
|
|
|
|
|
|
|
StepCountOver
|
Step count over
|
|
|
|
|
|
|
|
|
DebuggingInformationAcquisitionFailure
|
Failed to acquire debugging information
|
|
|
|
|
|
|
|
|
Note 1. | Applies to all of the following: MINICUBE2, E1Serial, and E20Serial. |
Note 2. | Applies to all of the following: MINICUBE, E1Jtag, E20Jtag, and MINICUBE2Jtag. |
Note 3. | This is only a break cause during trace. |
Note 4. | This is only a break cause during a break. |
[Example of use]
>>>debugger.GetBreakStatus()
Temporary
>>>a = debugger.GetBreakStatus()
Temporary
>>>print a
Temporary
>>>if (debugger.GetBreakStatus() == BreakStatus.Temporary):
... print "Temporary break"
...
Temporary
Temporary break
>>>
|