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8.2.1 Initialization routine for hardware

The initialization processing for hardware is configured by the following elements.

In the sample program, these elements are located in boot.asm.

 

(1)

RESET vector

A branch instruction to the entry point address of each processor element (PE) is allocated to the address where a branch of the program counter of each PE occurs when the microcontroller is reset. Since the RBASE register which holds the address of the RESET vector will hold a value in 512-byte units, the top of the RESET vector is aligned at the 512-byte boundary.

In the sample program, the RESET vector is located in the RESET_PEn section.

    .section "RESET_PE1", text
    .align   512
    jr32     __start ; RESET
    .align   16
    jr32     _Dummy  ; SYSERR
      :
    .align   16
    jr32     _Dummy_EI ; INTn(priority15)

 

The section name is optionally changeable, but it needs to be changed in conjunction with the -start option of the optimizing linker.

-start=RESET_PE1/01000000

Caution

For the address of the RESET vector, see the user's manual of the device.

 

When the branch destination at the reset of each PE is the same address, a single RESET_PEn section is used in common by each PE.

 

(2)

Interrupt handler table

When an exception handler address of the extended specifications (table lookup method) is used, the address of the exception handler routine in use is allocated to the corresponding element position in this table. Since the INTBP register which holds the table address will hold a value in 512-byte units, the top of the table is aligned at the 512-byte boundary.

In the sample program, the interrupt handler table is located in the EIINTTBL_PEn section.

    .section "EIINTTBL_PE1", const
    .align   512
    .dw      #_Dummy_EI ; INT0
    .dw      #_Dummy_EI ; INT1
    .dw      #_Dummy_EI ; INT2
    .rept    512 - 3
    .dw      #_Dummy_EI ; INTn
    .endm

Caution

For the maximum number of elements in the table, see the user's manual of the device.

 

The section name is optionally changeable, but it needs to be changed in conjunction with the INTBP register setting in the startup.

    mov     #__sEIINTTBL_PE1, r10
    ldsr    r10, 4, 1       ; set INTBP

(3)

Exception handler routine

This is a sample program for the exception handler routine of FE and EI levels. It repeats branches to itself without any operation.

Usually, it uses #pragma interrupt with the C source description.

    .align   2
_Dummy:
    br      _Dummy
_Dummy_EI:
    br      _Dummy_EI

(4)

Entry point

The entry point is the label (address) to which the RESET vector branches at a reset.

    .align   2
    .public  __start
__start:

(5)

Initialization of general-purpose registers

The general-purpose registers of each PE and the EIPC, CTPC, and FPEPC registers are initialized as a preparation to use the lockstep function.

    $nowarning
    mov     r0, r1
    $warning
    mov     r0, r2
    mov     r0, r3
     :
    mov     r0, r31
    ldsr    r0, 0, 0        ;  EIPC
    ldsr    r0, 16, 0       ;  CTPC

Since the FPEPC register can be initialized only after the FPU is enabled, it will be initialized later. See "Initial setting of FPU".

(6)

Branch to initialization processing for each PE

This branch is executed commonly by each PE. The PE reads its processor element number (PEID) and branches from that value to the initialization processing prepared for each PE.

    stsr    0, r10, 2       ; get HTCFG0
    shr     16, r10         ; get PEID
    cmp     1, r10
    bz      .L.entry_PE1
    cmp     2, r10
    bz      .L.entry_PE2
     :
    cmp     7, r10
    bz      .L.entry_PE7

This processing is not required for a program for a single core device.

(7)

__exit routine

The __exit routine repeats branches to itself to put PEs that are not in use to sleep.

__exit:
    br      __exit

(8)

Initialization processing for each PE

This is to initiate the hardware initialization processing (_hdwinit_PEn) prepared for each PE and the processing to make settings to use the exception handler address of extended specifications (table lookup method) and then branch to the initialization routine (_cstart_pmn) for the user program.

.L.entry_PE1:
    jarl    _hdwinit_PE1, lp        ; initialize hardware
    mov     #__sEIINTTBL_PE1, r6
    jar     _set_table_reference_method, lp ; set table reference method
    jr32    __cstart_pm1

(9)

Initialization processing for hardware

In the sample program, the RAM area is initialized as a preparation to use the ECC function. Global RAM and local RAM (for PE1) are initialized by the initialization processing for PE1 and local RAM (for PE2) is initialized by the initialization processing for PE2.

    .align  2
_hdwinit_PE1:
    mov     lp, r29                 ; save return address
    ; clear Global RAM
    mov     GLOBAL_RAM_ADDR, r6
    mov     GLOBAL_RAM_END, r7
    jarl    _zeroclr4, lp
    ; clear Local RAM PE1
    mov     LOCAL_RAM_PE1_ADDR, r6
    mov     LOCAL_RAM_PE1_END, r7
    jarl    _zeroclr4, lp
    mov     r29, lp
    jmp     [lp]
 
    .align  2
_hdwinit_PE2:
    mov     lp, r29                 ; save return address
    ; clear Local RAM PE2
    mov     LOCAL_RAM_PE2_ADDR, r6
    mov     LOCAL_RAM_PE2_END, r7
    jarl    _zeroclr4, lp
    mov     r29, lp
    jmp     [lp]
 
    .align  2
_zeroclr4:
    br      .L.zeroclr4.2
.L.zeroclr4.1:
    st.w    r0, [r6]
    add     4, r6
.L.zeroclr4.2:
    cmp     r6, r7
    bh      .L.zeroclr4.1
    jmp     [lp]

Caution

In the sample program, an invalid address is specified with a macro. For the RAM addresses to be initialized, see the user's manual of the device.

(10)

Processing to make settings to use exception handler address of extended specifications (table lookup method)

This processing sets the address of the interrupt handler table to the INTBP register and sets the interrupt control registers.

    .align  2
_set_table_reference_method:
    ldsr    r6, 4, 1        ; set INTBP
    mov     ICBASE, r10     ; get interrupt control register address
    set1    6, 0[r10]       ; set INT0 as table reference
    set1    6, 2[r10]       ; set INT1 as table reference
    set1    6, 4[r10]       ; set INT2 as table reference
    jmp     [lp]