The basic information defines CPU type: cpu, Base clock interval: tim_base, Base clock timer exception code: tim_intno, System stack size: sys_stksz, Whether to check stack: stkchk, Maximum priority: maxtpri, Maximum interrupt priority: maxintpri, Maximum number of interrupt handlers: maxint; Maximum value of exception code: maxintno.

Only one information item can be defined as basic information.

The following shows the basic information format.

[CPU_TYPE (chip_type);] [DEF_TIM (tim_base);] CLK_INTNO (tim_intno); SYS_STK (sys_stksz); [STK_CHK (stkchk);] [MAX_PRI (maxtpri);] [MAX_INTPRI (maxintpri);] MAX_INT (maxint [, maxintno ] );

The items constituting the basic information are as follows.

1 ) CPU type: cpu

Specifies the type for a CPU.
If you are using the CS +, don't need to specify this specified item.

The keyword that can be specified for chip_type is G3K or G3M or G3KH or G3MH.

G3K: G3K core

G3M: G3M core

G3KH: G3KH core

G3MH: G3MH core

If omitted The CPU type should be the device type specified in the -cpu option. When the PE number is specified in the -peid option, the CPU type corresponding to the PE number should be specified. When the -cpu option setting is omitted, the CPU type should be G3K.

2 ) Base clock interval: tim_base

Specifies the base clock interval (unit:millisecond) of the timer to be used.
A value from 0x1 to 0xffff can be specified for tim_base.

If omitted "0x1ms" is specified as the base clock cycle of the RI850V4.

Note The base clock cycle means the occurrence interval of base clock timer interrupt tim_intno, which is required for implementing the TIME MANAGEMENT FUNCTIONS provided by the RI850V4. To initialize hardware used by the RI850V4 for time management (such as timers and controllers), the setting must therefore be made so as to generate base clock timer interrupts at the interval defined with tim_base.

3 ) Base clock timer exception code: tim_intno

Specifies the exception code for the base clock timer interrupt that is necessary to implement the time management facility provided by the RI850V4.

The value that can be specified for tim_into is an interrupt source name specified in the device file or a value from 0x1000 to the maximum exception code maxintno.

Note When an interrupt source name is specified for tim_intno, -cpu D name must be specified for the CF850V4 activation option.

4 ) System stack size: sys_stksz

Specifies the system stack size (in bytes).
A value from 0x0 to 0x7ffffffc (aligned to a 4-byte boundary) can be specified for sys_stksz.

Note 1 For expressions to calculate the system stack size, refer to "1 System stack".

Note 2 The memory area for system stack is secured from the ".kernel_work section".

Note 3 The stack size that is actually secured is calculated as the specified stack size plus "20 + 80 (size of context area of interrupt handler)".

5 ) Whether to check stack: stkchk

Specifies whether to check the stack overflows before the RI850V4 starts processing.
The keyword that can be specified for flg is TA_ON or TA_OFF.

TA_ON: Overflow is checked

TA_OFF: Overflow is not checked

Note Overflow is not checked by default.

6 ) Maximum priority: maxtpri

Specifies the maximum priority of the task.
A value from 0x1 to 0x20 can be specified for maxtpri.

If omitted "0x20" is specified as the maximum task priority.

7 ) Maximum interrupt priority: maxintpri

Specifies the maximum priority for EI level maskable interrupts to be managed by the RI850V4.

The following values can be specified for maxintpri.

When the CPU type of the target device is G3K: A value from INTPRI0 to INTPRI7.

When the CPU type of the target device is G3M or G3KH or G3MH: A value from INTPRI0 to INTPRI15.

Note 1 When INTPRI3 is specified, the RI850V4 manages interrupts within the range from priority INTPRI3 to the minimum interrupt priority.
The minimum interrupt priority is determined as follows. When the CPU type of the target device is G3K: IINTPRI7 is the minimum interrupt priority.
When the CPU type of the target device is G3M or G3KH or G3MH: INTPRI15 is the minimum interrupt priority.

Note 2 When the interrupt handlers for the EI level maskable interrupts are called in the reduced mode (the RINT bit in the reset vector base address (RBASE) or the exception handler vector address (EBASE) is set to 1), the maximum interrupt priority should be set to INTPRI0.

If omitted The maximum interrupt priority is set to INTPRI0.

8 ) Maximum number of interrupt handlers: maxint; Maximum value of exception code: maxintno

A value from 0x0 to 0x200 can be specified for maxint, and a value from 0x1000 to 0x11ff can be specified for maxintno.

Note 1 Specify for maxint "the total number of interrupt handlers defined in the Interrupt handler information".

Note 2 When -cpu_name is specified as the CF850V4 activation option, the maxintno setting becomes invalid and the maximum exception code specified in the device file is used.