Selection of Optimum Instruction Format

5.1.8 Selection of Optimum Instruction Format

Some of the RX Family microcontroller instructions provide multiple instruction formats for an identical single processing.

The assembler selects the optimum instruction format that generates the shortest code according to the instruction and addressing mode specifications.

(1)	Immediate Value

For an instruction having an immediate value as an operand, the assembler selects the optimum one of the available addressing modes according to the range of the immediate value specified as the operand. The following shows the immediate value ranges in the order of priority.

Table 5.12

Ranges of Immediate Values

#imm	Decimal Notation	Hexadecimal Notation
#imm:1	1 to 2	1H to 2H
#imm:2	0 to 3	0H to 3H
#imm:3	0 to 7	0H to 7H
#imm:4	0 to 15	0H to 0FH
#imm:5	0 to 31	0H to 1FH
#imm:8	128 to 255	80H to 0FFH
#uimm:8	0 to 255	0H to 0FFH
#simm:8	128 to 127	80H to 7FH
#imm:16	32768 to 65535	8000H to 0FFFFH
#simm:16	32768 to 32767	8000H to 7FFFH
#simm:24	8388608 to 8388607	800000H to 7FFFFFH
#imm:32	2147483648 to 4294967295	80000000H to 0FFFFFFFFH

Notes 1.

Hexadecimal values can also be written in 32 bits.
Example: Decimal "127" = hexadecimal "7FH" can be written as "0FFFFFF81H".

Notes 2.

The #imm range for src in the INT instruction is 0 to 255.

Notes 3.

The #imm range for src in the RTSD instruction is four times the #uimm:8 range.

(2)	ADC and SBB Instructions

The following shows the ADC and SBB instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Note	The following table does not show the instruction formats and operands for which code selection is not optimized. When the processing size is not shown in the table, L is assumed.

Table 5.13

Instruction Formats of ADC and SBB Instructions

Instruction Format	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	src	src2	dest	Code Size [Bytes]
ADC src,dest	#simm:8		Rd	4
	#simm:16		Rd	5
	#simm:24		Rd	6
	#imm:32		Rd	7
ADC/SBB src,dest	dsp:8[Rs].L		Rd	4
ADC/SBB src,dest	dsp:16[Rs].L		Rd	5

In the SBB instruction, an immediate value is not allowed for src.

(3)	ADD Instruction

The following shows the ADD instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.14

Instruction Formats of ADD Instruction

Instruction Format	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	src	src2	dest	Code Size [Bytes]
(1) ADD src,dest	#uimm:4		Rd	2
	#simm:8		Rd	3
	#simm:16		Rd	4
	#simm:24		Rd	5
	#imm:32		Rd	6
	dsp:8[Rs].memex		Rd	3 (memex = UB), 4 (memex UB)
	dsp:16[Rs].memex		Rd	4 (memex = UB), 5 (memex UB)
(2) ADD src,src2,dest	#simm:8	Rs	Rd	3
	#simm:16	Rs	Rd	4
	#simm:24	Rs	Rd	5
	#imm:32	Rs	Rd	6

(4)	AND, OR, SUB, and MUL Instructions

The following shows the AND, OR, SUB, and MUL instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.15

Instruction Formats of AND, OR, SUB, and MUL Instructions

Instruction Format	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	src	src2	dest	Code Size [Bytes]
AND/OR/SUB/MUL src,dest	#uimm:4		Rd	2
	#simm:8		Rd	3
	#simm:16		Rd	4
	#simm:24		Rd	5
	#imm:32		Rd	6
	dsp:8[Rs].memex		Rd	3 (memex = UB), 4 (memex UB)
	dsp:16[Rs].memex		Rd	4 (memex = UB), 5 (memex UB)

In the SUB instruction, #simm:8/16/24 and #imm:32 are not allowed for src.

(5)	BMCnd Instruction

The following shows the BMCnd instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.16

Instruction Formats of BMCnd Instruction

Instruction Format	Processing Size	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	Processing Size	src	src2	dest	Code Size [Bytes]
BMCnd src,dest	B	#imm:3		dsp:8[Rs].B	4
BMCnd src,dest	B	#imm:3		dsp:16[Rs].B	5

(6)	CMP Instruction

The following shows the CMP instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.17

Instruction Formats of CMP Instruction

Instruction Format	Processing Size	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	Processing Size	src	src2	dest	Code Size [Bytes]
CMP src,src2	L	#uimm:4	Rd		2
	L	#uimm:8	Rd		3
	L	#simm:8	Rd		3
	L	#simm:16	Rd		4
	L	#simm:24	Rd		5
	L	#imm:32	Rd		6
	L	dsp:8[Rs].memex	Rd		3 (memex = UB), 4 (memex UB)
	L	dsp:16[Rs].memex	Rd		4 (memex = UB), 5 (memex UB)

(7)	DIV, DIVU, EMUL, EMULU, ITOF, MAX, MIN, TST, and XOR Instructions

The following shows the DIV, DIVU, EMUL, EMULU, ITOF, MAX, MIN, MUL, TST, and XOR instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.18

Instruction Formats of DIV, DIVU, EMUL, EMULU, ITOF, MAX, MIN, TST, and XOR Instructions

Instruction Format	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	src	src2	dest	Code Size [Bytes]
DIV/DIVU/ EMUL/EMULU/ITOF/ MAX/MIN/TST/XOR	#simm:8		Rd	4
	#simm:16		Rd	5
	#simm:24		Rd	6
	#imm:32		Rd	7
src,dest	dsp:8[Rs].memex		Rd	4 (memex = UB), 5 (memex UB)
src,dest	dsp:16[Rs].memex		Rd	5 (memex = UB), 6 (memex UB)

In the ITOF instruction, #simm:8/16/24 and #imm:32 are not allowed for src.

(8)	FADD, FCMP, FDIV, FMUL, and FTOI Instructions

The following shows the FADD, FCMP, FDIV, FMUL, and FTOI instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.19

Instruction Formats of FADD, FCMP, FDIV, FMUL, and FTOI Instructions

Instruction Format	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	src	src2	dest	Code Size [Bytes]
FADD/FCMP/FDIV/ FMUL/FTOI src,dest	#imm:32		Rd	7
	dsp:8[Rs].L		Rd	4
	dsp:16[Rs].L		Rd	5

In the FTOI instruction, #imm:32 is not allowed for src.

(9)	MVTC, STNZ, and STZ Instructions

The following shows the MVTC, STNZ, and STZ instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.20

Instruction Formats of MVTC, STNZ, and STZ Instructions

Instruction Format	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	src	src2	dest	Code Size [Bytes]
MVTC/STNZ/STZ src,dest	#simm:8		Rd	4
	#simm:16		Rd	5
	#simm:24		Rd	6
	#imm:32		Rd	7

(10)	MOV Instruction

The following shows the MOV instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.21

Instruction Formats of MOV Instruction

Instruction Format	size	Processing Size	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	size	Processing Size	src	src2	dest	Code Size [Bytes]
MOV(.size) src,dest	B/W/L	size	Rs (Rs=R0-R7)		dsp:5[Rd] (Rd=R0-R7)	2
	B/W/L	L	dsp:5[Rs] (Rs=R0-R7)		Rd (Rd=R0-R7)	2
	B/W/L	L	#uimm:8		dsp:5[Rd] (Rd=R0-R7)	3
	L	L	#uimm:4		Rd	2
	L	L	#uimm:8		Rd	3
	L	L	#simm:8		Rd	3
	L	L	#simm:16		Rd	4
	L	L	#simm:24		Rd	5
	L	L	#imm:32		Rd	6
	B	B	#imm:8		[Rd]	3
	W/L	W/L	#simm:8		[Rd]	3
	W	W	#imm:16		[Rd]	4
	L	L	#simm:16		[Rd]	4
	L	L	#simm:24		[Rd]	5
	L	L	#imm:32		[Rd]	6
	B	B	#imm:8		dsp:8[Rd]	4
	W/L	W/L	#simm:8		dsp:8[Rd]	4
MOV(.size) src,dest	W	W	#imm:16		dsp:8[Rd]	5
	L	L	#simm:16		dsp:8[Rd]	5
	L	L	#simm:24		dsp:8[Rd]	6
	L	L	#imm:32		dsp:8[Rd]	7
	B	B	#imm:8		dsp:16[Rd]	5
	W/L	W/L	#simm:8		dsp:16[Rd]	5
	W	W	#imm:16		dsp:16[Rd]	6
	L	L	#simm:16		dsp:16[Rd]	6
	L	L	#simm:24		dsp:16[Rd]	7
	L	L	#imm:32		dsp:16[Rd]	8
	B/W/L	L	dsp:8[Rs]		Rd	3
	B/W/L	L	dsp:16[Rs]		Rd	4
	B/W/L	size	Rs		dsp:8[Rd]	3
	B/W/L	size	Rs		dsp:16[Rd]	4
	B/W/L	size	[Rs]		dsp:8[Rd]	3
	B/W/L	size	[Rs]		dsp:16[Rd]	4
	B/W/L	size	dsp:8[Rs]		[Rd]	3
	B/W/L	size	dsp:16[Rs]		[Rd]	4
	B/W/L	size	dsp:8[Rs]		dsp:8[Rd]	4
	B/W/L	size	dsp:8[Rs]		dsp:16[Rd]	5
	B/W/L	size	dsp:16[Rs]		dsp:8[Rd]	5
	B/W/L	size	dsp:16[Rs]		dsp:16[Rd]	6

(11)	MOVU Instruction

The following shows the MOVU instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.22

Instruction Formats of MOVU Instruction

Instruction Format	size	Processing Size	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	size	Processing Size	src	src2	dest	Code Size [Bytes]
MOVU(.size) src,dest	B/W	L	dsp:5[Rs] (Rs=R0-R7)		Rd (Rd=R0-R7)	2
	B/W	L	dsp:8[Rs]		Rd	3
	B/W	L	dsp:16[Rs]		Rd	4

(12)	PUSH Instruction

The following shows the PUSH instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.23

Instruction Formats of PUSH Instruction

Instruction Format	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	src	src2	dest	Code Size [Bytes]
PUSH src	dsp:8[Rs]			3
PUSH src	dsp:16[Rs]			4

(13)	ROUND Instruction

The following shows the ROUND instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.24

Instruction Formats of ROUND Instruction

Instruction Format	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	src	src2	dest	Code Size [Bytes]
ROUND src,dest	dsp:8[Rs]		Rd	4
ROUND src,dest	dsp:16[Rs]		Rd	5

(14)	SCCnd Instruction

The following shows the SCCnd instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.25

Instruction Formats of SCCnd Instruction

Instruction Format	size	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	size	src	src2	dest	Code Size [Bytes]
SCCnd(.size) src,dest	B/W/L			dsp:8[Rd]	4
SCCnd(.size) src,dest	B/W/L			dsp:16[Rd]	5

(15)	XCHG Instruction

The following shows the XCHG instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.26

Instruction Formats of XCHG Instruction

Instruction Format	Processing Size	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	Processing Size	src	src2	dest	Code Size [Bytes]
XCHG src,dest	L	dsp:8[Rs].memex		Rd	4(memex = UB), 5(memex UB)
XCHG src,dest	L	dsp:16[Rs].memex		Rd	5(memex = UB), 6(memex UB)

(16)	BCLR, BNOT, BSET, and BTST Instructions

The following shows the BCLR, BNOT, BSET, and BTST instruction formats and operands for which the assembler selects the optimum code, in the order of selection priority.

Table 5.27

Instruction Formats of BCLR, BNOT, BSET, and BTST Instructions

Instruction Format	Processing Size	Target of Optimum Selection			Code Size [Bytes]
Instruction Format	Processing Size	src	src2	dest	Code Size [Bytes]
BCLR/BNOT/BSET/BTST src,dest	B	#imm:3		dsp:8[Rd].B	3
	B	#imm:3		dsp:16[Rd].B	4
	B	Rs		dsp:8[Rd].B	4
	B	Rs		dsp:16[Rd].B	5