shr | CS+ V4.01.00

shr

Logical right shift.

[Syntax]

-	shr reg1, reg2

-	shr imm5, reg2

-	shr reg1, reg2, reg3

The following can be specified for imm5:

-	Absolute expression having a value of up to 5 bits

[Function]

-	Syntax "shr reg1, reg2"

Logically shifts to the right the value of the register specified by the second operand by the number of bits indicated by the lower 5 bits of the register value specified by the first operand, then stores the result in the register specified by the second operand.

-	Syntax "shr imm5, reg2"

Logically shifts to the right the value of the register specified by the second operand by the number of bits specified by the value of the absolute expression specified by the first operand, then stores the result in the register specified by the second operand.

-	Syntax "shr reg1, reg2, reg3"

[Description]

The assembler generates one shr machine instruction.

[Flag]

CY	1 if the value of the bit shifted out last is 1, 0 if not (0 if the specified number of bits is 0)
OV	0
S	1 if the result is negative, 0 if not
Z	1 if the result is 0, 0 if not
SAT	---

[Caution]

-	If an absolute expression having a value exceeding the range of 0 to 31 is specified as imm5 in syntax "shr imm5, reg2", the assembler outputs the following message, and continues assembling by using the lower 5 bitsNote of the specified value.

W0550011 : illegal operand (range error in immediate).

Note	The shr machine instruction takes an immediate value of 0 to 31 (0x0 to 0x1F) as the first operand.