sar | CS+ V4.01.00

sar

Arithmetic right shift.

[Syntax]

-	sar reg1, reg2

-	sar imm5, reg2

-	sar reg1, reg2, reg3

The following can be specified for imm5:

-	Absolute expression having a value of up to 5 bits

[Function]

-	Syntax "sar reg1, reg2"

Arithmetically shifts to the right the value of the register specified by the second operand by the number of bits indicated by the lower 5 bits of the register value specified by the first operand, then stores the result in the register specified by the second operand.

-	Syntax "sar imm5, reg2"

Arithmetically shifts to the right the value of the register specified by the second operand by the number of bits specified by the value of the absolute expression specified by the first operand, then stores the result in the register specified by the second operand.

-	Syntax "sar reg1, reg2, reg3"

[Description]

The assembler generates one sar machine instruction.

[Flag]

CY	1 if the value of the bit shifted out last is 1, 0 if not (0 if the specified number of bits is 0)
OV	0
S	1 if the result is negative, 0 if not
Z	1 if the result is 0, 0 if not
SAT	---

[Caution]

-	If an absolute expression having a value exceeding the range of 0 to 31 is specified for imm5 in syntax "sar imm5, reg2", the assembler outputs the following message, and continues assembling using the lower 5 bitsNote of the specified value.

W0550011 : illegal operand (range error in immediate).

Note	The sar machine instruction takes an immediate value of 0 to 31 (0x0 to 0x1F) as the first operand.