Floating-point compare (double)
The following can be specified for imm4:
The content in double-precision floating-point format in the register pair specified by reg2 is compared with the content in double-precision floating-point format in the register pair specified by reg1, via the imm4 comparison condition. The result (1 if true; 0 if false) is set in the condition bit (CC(7:0) bits; bits 31-24) in the FPSR register specified via cc#3. If cc#3 is omitted, it is set in the CC0 bit (bit 24).
Via cmpfcnd.d, a corresponding "cmpf.d" instruction is generated (see "Table 5.50 cmpfcnd.d Instruction List" for details), and expanded in the format "cmpf.d imm4, reg1, reg2, cc#3". The content in single-precision floating-point format in the register pair specified by reg2 is compared with the content in single-precision floating-point format in the register pair specified by reg1, via the comparison condition. The result (1 if true; 0 if false) is set in the condition bit (CC(7:0) bits; bits 31-24) in the FPSR register specified via cc#3. If cc#3 is omitted, it is set in the CC0 bit (bit 24).
If the instruction is executed in syntax "cmpf.d imm4, reg1, reg2, cc#3", the assembler generates one cmpf.d machine instruction. |
If the instruction is executed in syntax "cmpfcnd.d reg1, reg2", the assembler generates the corresponding cmpf.d instruction (see "Table 5.50 cmpfcnd.d Instruction List") and expands it to syntax "cmpf.d imm4, reg1, reg2, cc#3". |
If an absolute expression having a value exceeding 4 bits is specified as imm4 of the cmpf.d instruction, the following message is output, and assembly continues using the lower 4 bits of the specified value. |