FE level software exception (FE-level Trap)
Saves the contents of the return PC (address of the instruction next to the FETRAP instruction) and the current contents of the PSW to FEPC and FEPSW, respectively, stores the exception cause code in the FEIC register, and updates the PSW according to the exception causes. Execution then branches to the exception handler address and exception handling is started.
Table 5.42 Correspondence between vector4 and Exception Cause Codes and Exception Handler Address Offset shows the correspondence between vector4 and exception cause codes and exception handler address offset. Exception handler addresses are calculated based on the offset addresses listed in Table 5.42 Correspondence between vector4 and Exception Cause Codes and Exception Handler Address Offset.