Reserved Instruction exception (Reserved Instruction Exception)
The following can be specified as imm5:
The following can be specified as imm4:
Saves the contents of the return PC (address of the RIE instruction) and the current contents of the PSW to FEPC and FEPSW, respectively, stores the exception cause code in the FEIC register, and updates the PSW according to the exception causes. Execution then branches to the exception handler address and exception handling is started.
Exception handler addresses are calculated based on the offset address 60H.