divhu | CS+ V4.01.00

divhu

Divides unsigned half-word.

[Syntax]

-	divhu reg1, reg2, reg3

-	divhu imm, reg2, reg3

The following can be specified for imm:

-	Absolute expression having a value of up to 16 bitsNote

-	Relative expression

Note	The assembler does not check whether the value of the expression exceeds 16 bits. The generated machine instruction uses only the lower 16 bits for execution.

[Function]

-	Syntax "divhu reg1, reg2, reg3"

Divides the register value specified by the second operand by the value of the lower halfword data of the register value specified by the first operand as an unsigned value and stores the quotient in the register specified by the second operand, and the remainder in the register specified by the third operand. If the same register is specified by the second and third operands, the remainder is stored in that register.

-	Syntax "divhu imm, reg2, reg3"

Divides the register value specified by the second operand by the value of the lower halfword data of the absolute or relative expression specified by the first operand as an unsigned value and stores the quotient in the register specified by the second operand, and the remainder in the register specified by the third operand. If the same register is specified by the second and third operands, the remainder is stored in that register.

[Description]

-	If the instruction is executed in syntax "divhu reg1, reg2, reg3", the assembler generates one divhu machine instruction.

-	If the instruction is executed in syntax "divhu imm, reg2, reg3", and the following expression is specified for imm, the assembler executes instruction expansion to generate one or more machine instructionsNote.

(a)

divhu   0, reg2, reg3

divhu   r0, reg2, reg3

(b)	Absolute expression having a value of other than 0 within the range of -16 to +15

divhu   imm5, reg2, reg3

mov     imm5, r1

divhu   r1, reg2, reg3

(c)	Absolute expression exceeding the range of -16 to +15, but within the range of -32,768 to +32,767

divhu   imm16, reg2, reg3

movea   imm16, r0, r1

divhu   r1, reg2, reg3

(d)	Absolute expression having a value exceeding the range of -32,768 to +32,767

If all the lower 16 bits of the value of imm are 0

divhu   imm, reg2, reg3

movhi   HIGHW(imm), r0, r1

divhu   r1, reg2, reg3

Else

divhu   imm, reg2, reg3

mov     imm, r1

divhu   r1, reg2, reg3

(e)	Relative expression having !label or %label, or that having $label for a label having a definition in the sdata/sbss-attribute section

divhu   !label, reg2, reg3

movea   !label, r0, r1

divhu   r1, reg2, reg3

divhu   %label, reg2, reg3

movea   %label, r0, r1

divhu   r1, reg2, reg3

divhu   $label, reg2, reg3

movea   $label, r0, r1

divhu   r1, reg2, reg3

(f)	Relative expression having #label or label, or that having $label for a label having no definition in the sdata/sbss-attribute section

divhu   #label, reg2, reg3

mov     #label, r1

divhu   r1, reg2, reg3

divhu   label, reg2, reg3

mov     label, r1

divhu   r1, reg2, reg3

divhu   $label, reg2, reg3

mov     $label, r1

divhu   r1, reg2, reg3

Note	The divhu machine instruction does not take an immediate value as an operand.

[Flag]

CY	---
OV	1 if Integer-Overflow occurs, 0 if not
S	1 if the word data MSB of the result is 1, 0 if not
Z	1 if the result is 0, 0 if not
SAT	---