divqu


Division of (unsigned) word data (variable steps) (Divide Word Unsigned Quickly)

[Syntax]

-

divqu reg1, reg2, reg3

[Function]

Divides the word data in general-purpose register reg2 by the word data in general-purpose register reg1, stores the quotient in reg2, and stores the remainder in general-purpose register reg3. General-purpose register reg1 is not affected.

The minimum number of steps required for division is determined from the values in reg1 and reg2, then this operation is executed.

When division by zero occurs, an overflow results and all operation results except for the OV flag are undefined.

[Description]

-

The assembler generates one divqu machine instruction.

[Flag]

CY

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OV

"1" when overflow occurs; otherwise, "0"

S

"1" when the MSB in the word data of the operation result quotient is a negative value; otherwise, "0"

Z

"1" when operation result quotient is a "0"; otherwise, "0"

SAT

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