FADD | CS+ V7.00.00

FADD	Floating-point addition	FADD
	Floating-point ADD

[Syntax]

(1)	FADD src, dest

(2)	FADD src, src2, dest [V2.01.00 or later]

[Operation]

(1)	dest = dest + src;

(2)	dest = src + src2; [V2.01.00 or later]

[Function]

(1)	This instruction adds the single-precision floating-point numbers stored in dest and src and places the result in dest.

(2)

This instruction adds the single-precision floating-point numbers stored in src2 and src and places the result in dest. You can assemble assembly-language code that includes this instruction if you have specified the assembler option -isa with selection of the instruction set of the RXv2 or a later version. [V2.01.00 or later]

-	Rounding of the result is in accord with the setting of the RM[1:0] bits in the FPSW.

-	Handling of denormalized numbers depends on the setting of the DN bit in the FPSW.

-	The operation result is +0 when the sum of (src and dest) and (src and src2) of the opposite signs is exactly 0 except in the case of a rounding mode towards -∞. The operation result is -0 when the rounding mode is towards -∞.

[Instruction Format]

Syntax	Processng Size	Operand			Code Size (Byte)
Syntax	Processng Size	src	src2	dest	Code Size (Byte)
(1) FADD src, dest	L	#IMM:32	−	Rd	7
	L	Rs	−	Rd	3
	L	[Rs].L	−	Rd	3
	L	dsp:8[Rs].L*	−	Rd	4
	L	dsp:16[Rs].L*	−	Rd	5
(2) FADD src, src2, dest [V2.01.00 or later]	L	Rs	Rs2	Rd	3

Note

* For the RX Family assembler manufactured by Renesas Electronics Corp., enter a scaled value (the actual value multiplied by 4) as the displacement value (dsp:8, dsp:16). With dsp:8, values from 0 to 1020 (255 × 4) can be specified; with dsp:16, values from 0 to 262140 (65535 × 4) can be specified. The value divided by 4 will be stored in the instruction code.

[Flag Change]

Flag

Change

–

Conditions

Z : The flag is set if the result of the operation is +0 or -0; otherwise it is cleared.

S : The flag is set if the sign bit (bit 31) of the result of the operation is 1; otherwise it is cleared.

CV : The flag is set if an invalid operation exception is generated; otherwise it is cleared.

CO : The flag is set if an overflow exception is generated; otherwise it is cleared.

CZ : The value of the flag is always 0.

CU : The flag is set if an underflow exception is generated; otherwise it is cleared.

CX : The flag is set if an inexact exception is generated; otherwise it is cleared.

CE : The flag is set if an unimplemented processing is generated; otherwise it is cleared.

FV : The flag is set if an invalid operation exception is generated, and otherwise left unchanged.

FO : The flag is set if an overflow exception is generated, and otherwise left unchanged.

FU : The flag is set if an underflow exception is generated, and otherwise left unchanged.

FX : The flag is set if an inexact exception is generated, and otherwise left unchanged.

Note	The FX, FU, FO, and FV flags do not change if any of the exception enable bits EX, EU, EO, and EV is 1. The S and Z flags do not change when an exception is generated.

[Description Example]

FADD R1, R2

FADD [R1], R2

FADD R1, R2, R3