[Syntax]

MSBLH src, src2, Adest

[Operation]

signed short tmp1, tmp2;

signed 72bit tmp3;

tmp1 = (signed short) src;

tmp2 = (signed short) (src2 >> 16);

tmp3 = (signed long) tmp1 * (signed long) tmp2;

Adest = Adest - (tmp3 << 16);

[Function]

This instruction multiplies the lower-order 16 bits of src by the higher-order 16 bits of src2, and subtracts the result from the value in the accumulator (ACC0 or ACC1). The subtraction is performed with the least significant bit of the result of multiplication corresponding to bit 16 of ACC. The result of subtraction is stored in ACC. The lower-order 16 bits of src and the higher-order 16 bits of src2 are treated as signed integers. You can assemble assembly-language code that includes this instruction if you have specified the assembler option -isa with selection of the instruction set of the RXv2 or a later version.

[Instruction Format]

[Flag Change]

This instruction does not affect the states of flags.

[Description Example]

MSBLH R1, R2, A1