This instruction divides the single-precision floating-point number stored in dest by that stored in src and places the result in dest. Rounding of the result is in accord with the setting of the RM[1:0] bits in the FPSW. |
Z : The flag is set if the result of the operation is +0 or -0; otherwise it is cleared.
S : The flag is set if the sign bit (bit 31) of the result of the operation is 1; otherwise it is cleared.
CV : The flag is set if an invalid operation exception is generated; otherwise it is cleared.
CO : The flag is set if an overflow exception is generated; otherwise it is cleared.
CZ : The flag is set if a division-by-zero exception is generated; otherwise it is cleared.
CU : The flag is set if an underflow exception is generated; otherwise it is cleared.
CX : The flag is set if an inexact exception is generated; otherwise it is cleared.
CE : The flag is set if an unimplemented processing exception is generated; otherwise it is cleared.
FV : The flag is set if an invalid operation exception is generated; otherwise it does not change.
FO : The flag is set if an overflow exception is generated; otherwise it does not change.
FZ : The flag is set if a division-by-zero exception is generated; otherwise it does not change.
FU : The flag is set if an underflow exception is generated; otherwise it does not change.
FX : The flag is set if an inexact exception is generated; otherwise it does not change.
The FX, FU, FZ, FO, and FV flags do not change if any of the exception enable bits EX, EU, EZ, EO, and EV is 1. The S and Z flags do not change when an exception is generated. |