[Syntax]

MULLH src, src2, Adest

[Operation]

signed short tmp1, tmp2;

signed 72bit tmp3;

tmp1 = (signed short) src;

tmp2 = (signed short) (src2 >> 16);

tmp3 = (signed long) tmp1 * (signed long) tmp2;

Adest = (tmp3 << 16);

[Function]

This instruction multiplies the lower-order 16 bits of src by the higher-order 16 bits of src2, and stores the result in the accumulator (ACC0 or ACC1). When the result is stored, the least significant bit of the result corresponds to bit 16 of ACC, and the section corresponding to bits 71 to 48 of ACC is sign-extended. Moreover, bits 15 to 0 of ACC are cleared to 0. The lower-order 16 bits of src and the higher-order 16 bits of src2 are treated as signed integers. You can assemble assembly-language code that includes this instruction if you have specified the assembler option -isa with selection of the instruction set of the RXv2 or a later version.

[Instruction Format]

[Flag Change]

This instruction does not affect the states of flags.

[Description Example]

MULLH R1, R2, A1